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pentium ? iii processor mobile module: mobile module connector 2 (mmc-2) featuring intel ? speedstep ? technology datasheet product features mobile pentium iii processor featuring intel speedstep technology with processor speeds of 750/600 mhz, 700/550 mhz, 650/500 mhz, and 600/500 mhz on-die, primary 16-k instruction cache and 16-k write back data cache on-die, 256-k l2 cache ? eight-way set associative ? runs at the speed of the processor core fully compatible with previous intel mobile microprocessors ? binary compatible with all applications ? support for mmx ? technology supports streaming simd power management features that provide low-power dissipation ? quick start mode ? deep sleep mode integrated math co-processor integrated active thermal feedback (atf) system programmable trip point interrupt or poll mode for temperature reading intel 82443bx host bridge system controller ? dram controller supports 3.3-v sdram at 100 mhz ? supports pci clkrun# protocol ? sdram clock enable support and self- refresh of sdram during suspend mode ? pci bus control 3.3v only, pci specification, revision 2.1 compliant supports single agp 66-mhz, 3.3-v device two-piece thermal transfer plate (ttp) for heat dissipation ? the cpu ttp is made of nickel-plated copper ? the bx ttp is made of aluminum mobile pentium iii processor core voltage regulation supports input voltages from 7.5v to 21.0v dc ? above 80% peak efficiency ? integrated vr solution 243356-005
243356-005 datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium iii processor mobile module featuring intel speedstep technology may contain design defects or errors known as erra ta, which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2000 *other brands and names are the property of their respective owners.
243356-005 datasheet iii pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology contents 1.0 introduction................................................................................................................ ......... 1 1.1 references ............................................................................................................ 1 2.0 architecture overview ....................................................................................................... .3 3.0 signal information .......................................................................................................... ....5 3.1 signal definitions................................................................................................... 5 3.1.1 signal list.................................................................................................6 3.1.2 memory signal description ...................................................................... 7 3.1.3 agp signals ............................................................................................. 8 3.1.4 pci signals.............................................................................................10 3.1.5 intel speedstep technology signals .....................................................11 3.1.6 processor and piix4e/m sideband signals ...........................................12 3.1.7 power management signals ..................................................................13 3.1.8 clock signals..........................................................................................14 3.1.9 voltage signals ......................................................................................15 3.1.10 itp and jtag pins.................................................................................16 3.1.11 miscellaneous pins.................................................................................16 3.2 connector pin assignments ................................................................................17 3.3 pin and pad assignments ...................................................................................19 4.0 functional description...................................................................................................... 21 4.1 pentium iii processor mobile module featuring intel speedstep technology ...21 4.2 l2 cache .............................................................................................................21 4.3 the 82443bx host bridge system controller .....................................................21 4.3.1 memory organization .............................................................................21 4.3.2 reset strap options ...............................................................................22 4.3.3 pci interface ..........................................................................................22 4.3.4 agp interface.........................................................................................23 4.4 intel speedstep technology ...............................................................................23 4.5 power management ............................................................................................23 4.5.1 clock control architecture......................................................................23 4.5.1.1 normal state .............................................................................25 4.5.1.2 auto halt state ..........................................................................25 4.5.1.3 stop grant state........................................................................26 4.5.1.4 quick start state .......................................................................26 4.5.1.5 halt/grant snoop state ..........................................................27 4.5.1.6 sleep state ................................................................................27 4.5.1.7 deep sleep state ......................................................................27 4.6 power consumption in power management modes ...........................................28 5.0 electrical specifications................................................................................................... .31 5.1 system bus clock signal quality specifications.................................................31 5.1.1 bclk dc specifications.........................................................................31 5.1.2 bclk ac specifications.........................................................................31 5.2 system power requirements..............................................................................33 5.3 processor core voltage regulation ....................................................................33
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology iv datasheet 243356-005 5.3.1 voltage regulator efficiency .................................................................. 34 5.3.2 voltage regulator control ...................................................................... 36 5.3.3 power planes: bulk capacitance requirements.................................... 38 5.3.4 system power supply circuit protection................................................ 40 5.3.4.1 dc power system protection.................................................... 40 5.3.4.2 v_dc power supply.................................................................. 41 5.3.4.3 overcurrent protection .............................................................. 41 5.3.4.4 current limit shift point ............................................................ 43 5.3.4.5 slew rate control ..................................................................... 45 5.3.4.6 undervoltage lockout ............................................................... 47 5.3.4.7 overvoltage lockout ................................................................. 48 5.4 active thermal feedback ................................................................................... 52 5.5 thermal sensor configuration register.............................................................. 52 6.0 mechanical specifications................................................................................................ 53 6.1 mobile module dimensions ................................................................................. 53 6.1.1 pin 1 location of the mmc-2 connector ................................................ 53 6.1.2 printed circuit board .............................................................................. 54 6.1.3 height restrictions ................................................................................. 55 6.2 thermal transfer plate ....................................................................................... 55 6.3 mobile module physical support......................................................................... 57 6.3.1 mobile module mounting requirements................................................. 57 6.3.2 weight .................................................................................................... 58 7.0 thermal specification....................................................................................................... 59 7.1 thermal design power........................................................................................ 59 8.0 labeling information........................................................................................................ .60 9.0 environmental standards................................................................................................. 62 figures 1 block diagram...................................................................................................... 4 2 mmc-2 connector pad footprint ........................................................................ 20 3 clock control states ........................................................................................... 25 4 bclk waveform at the processor core pins ..................................................... 32 5 vr efficiency chart for vcore at 1.60v .............................................................. 35 6 vr efficiency chart for vcore at 1.35v ............................................................... 35 7 power sequence timing ..................................................................................... 38 8 v_dc rms ripple current ................................................................................. 40 9 v_dc power system protection block diagram................................................. 41 10 overcurrent protection circuit............................................................................. 42 11 current shift model ............................................................................................. 43 12 undervoltage lockout ......................................................................................... 47 13 undervoltage lockout model .............................................................................. 48 14 overvoltage lockout ........................................................................................... 49 15 overvoltage lockout model ................................................................................ 49 16 recommended power supply protection circuit for the system electronics ..... 51 17 simulation of v_dc voltage skew...................................................................... 51 18 board dimensions and mmc-2 connector orientation....................................... 53
243356-005 datasheet v pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 19 board dimensions and mmc-2 connector?pin 1 orientation ...........................54 20 printed circuit board thickness ..........................................................................54 21 height restrictions .............................................................................................55 22 82443bx thermal transfer plate (reference only) ..........................................56 23 82443bx thermal transfer plate detail..............................................................56 24 cpu thermal transfer plate (reference only)...................................................57 25 standoff holes, board edge clearance, and emi containment ring .................58 26 product tracking code........................................................................................61 tables 1 connector signal summary .................................................................................. 5 2 memory signal descriptions.................................................................................. 7 3 agp signal descriptions ....................................................................................... 8 4 pci signal descriptions.......................................................................................10 5 intel speedstep technology signal description .................................................11 6 processor and piix4e/m sideband signal descriptions .....................................12 7 power management signal descriptions ............................................................13 8 clock signal descriptions....................................................................................14 9 voltage descriptions ...........................................................................................15 10 itp and jtag pins..............................................................................................16 11 miscellaneous pin descriptions...........................................................................16 12 connector pin assignment..................................................................................17 13 connector specifications.....................................................................................20 14 configuration straps for the 82443bx host bridge system controller ...............22 15 clock state characteristics .................................................................................24 16 power consumption values i ..............................................................................28 17 power consumption values ii .............................................................................29 18 power consumption values iii ............................................................................29 19 bclk dc specifications......................................................................................30 20 bclk ac specifications at the processor core pins..........................................30 21 bclk signal quality ac specifications at the processor core...........................31 22 system power requirements..............................................................................32 23 vcore power conversion efficiency at 1.60v......................................................33 24 vcore power conversion efficiency at 1.35v......................................................33 25 voltage signal definitions and sequences .........................................................35 26 vr_on in-rush current.......................................................................................36 27 bulk capacitance requirements per power plane .............................................38 28 thermal sensor smbus address ........................................................................51 29 thermal sensor configuration register ..............................................................51 30 thermal design power (tdpmodule) specification ........................................58 31 environmental standards ....................................................................................61
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology vi datasheet 243356-005 revision history date revision updates january 2000 1.0 initial release february 2000 2.0 revision 2.0 contains the following updates: added section 4.6, which now contains the power consumption values in power management modes updated sections 5.1 and 5.2 for accuracy and clarity changed the name of section 5.3.4 to ?system power supply circuit guidelines? updated figure 16. all ?pw? references were changed to ?v_dc? added a note in figure 18 for clarification added a note in figure 23 for clarification specification clarifications were made to section 6.2 specification clarifications were made to section 6.3.1 april 2000 3.0 revision 3.0 contains the following updates: added new 700/550-mhz processor speed added table 17, ?power consumption values ii? in table 20, ?bclk signal quality ac specifications at the processor core? note 3 was updated for clarification in table 21, ?system power requirements? the vcpupu minimal, nominal, and maximum values were corrected added maximum and minimum designators to figure 4, ?bclk waveform at the processor core pins? for clarity rewrote section 5.3.3, ?power planes: bulk capacitance requirements? for clarity added 700/550 mhz tdpmodule values to table 29, ?thermal design power specifications april 2000 4.0 revision 4.0 contains the following updates: added product tracking codes (ptcs) for conversion modules. see table 17, ?power consumption values ii? may 2000 5/0 revision 5.0 contains the following updates: added 750/600 mhz added table 18, ?power consumption values iii?, which contains the power management data for c-step.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 1 1.0 introduction this document provides the technical specifications for integrating the intel pentium iii processor mobile module with intel speedstep technology connector 2 (mmc-2) into the latest notebook systems for today?s notebook market. building around this design gives the system manufacturer these advantages: avoids complexities associated with designing high-speed processor core logic boards. a standard interface provides an upgrade path from previous intel mobile modules. 1.1 references refer to the following documents for additional information relating to the pentium iii processor mobile module with featuring intel speedstep technology. mobile pentium? iii processor in bga2 and micro-pga2 packages datasheet (order number 245302) intel ? 440bx agpset: 82443bx host bridge/controller datasheet (order number: 290633- 001) 82371ab pci-to-isa/ide xcelerator (piix4) (order number: 290562-001) intel ? 82371mb (piix4e/m) specification update* ck97 clock synthesizer/driver specification (or-1089) intel ? pentium ? iii processor mobile module mmc-2 simulation and validation kit rev. 2.0 (or-1781) intel ? pentium ? iii processor mobile module system electronics 100-mhz layout guidelines rev. 1.0 (or-1780) mobile pentium ? iii processor/440bx agpset recommended design and debug practices (rddp-a) 100 mhz rev. 2.0 (sc-2760) 66/100mhz pc sdram unbuffered so-dimm specification rev 1.0* intel ? mobile module design guide (ap-590) pentium ? ii processor mobile module mmc-2 insertion & extraction user manual rev 1.0* mobile pentium ? ii processor mobile module 400-pin bga connector assembly development guide rev. 1.0* focused discussion on intel ? mobile modules design for mfg. & best methods for mhpg customers rev. 1.0 (or-1385) emi design guide (ormd6-0859) intel ? mobile module newsletters* intel ? mobile module thermal diode temperature sensor application note* geyserville hardware technical specification, revision 2.0 (or-1728) geyserville software architecture specification, revision 1.5 (sc-2364) intel ? mmc-2 standoff/receptacle height spreadsheet*
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 2 datasheet 243356-005 agp interface specification revision 2.0* * available now, contact your intel field representative
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 3 2.0 architecture overview a highly integrated assembly, the pentium iii processor mobile module featuring intel speedstep technology contains the mobile pentium iii processor core that runs at speeds of 750/600 mhz, 700/550 mhz, 650/500, and 600/500 mhz with a 100-mhz processor system bus speed (psb). the intel 440bx agpset provides immediate system-level support and includes the piix4e/m pci/isa bridge and the 82443bx host bridge. the piix4e/m provides extensive power management capabilities and supports the intel 82443bx host bridge. a notebook?s system electronics must include a piix4e/m device to connect to the mobile module. key features of the intel 82443bx host bridge include: the dram controller supporting sdram at 3.3vwith a burst read at 4-1-1-1; a pci clkrun# signal to request the piix4e/m to regulate the pci clock on the pci bus; the 82443bx clock enables self-refresh mode of sdram during suspend mode and is compatible with smram (c_smram) and extended smram (e_smram) modes of power management; and e_smram mode supports write-back cacheable smram up to 1 mb. the ttps on the mobile pentium iii processor and the 82443bx host bridge provide heat dissipation and thermal attach points for the manufacturer?s thermal solution. an on-board voltage regulator converts the system dc voltage to the processor?s core and i/o voltage. isolating the processor voltage requirements allows the system manufacturer to incorporate different processor variants into a single notebook system. supporting input voltages from 7.5v to 21.0v, the integrated module voltage regulator enables an above 80% peak efficiency and de-couples the processor voltage requirements from the system. also incorporated is active thermal feedback (atf) sensing, compliant to the acpi specification rev 1.0. an integrated system management bus (smbus) compliant thermal sensor supports the internal and external temperature sensing with programmable trip points. figure 1 illustrates the block diagram of the pentium iii processor mobile module featuring intel speedstep technology.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 4 datasheet 243356-005 figure 1. block diagram 400-pin, board-to-board connector cpu voltage regulator memory bus 82443bx "northbridge" (v_3) atf sense m obile pentium iii processor core r - g t l speedstep control logic (v_3) piix4e/m sidebands sideband pullup (v_cpupu) v_dc (7.5v~21.0v dc) processor core voltage vtt gclko gclki hclk0 psb vr control agp bus pclk pci bus memory bus dclko dclkwr smbus piix4e/m sidebands hi/lo # vtt clock driver (v_clk) speedstep
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 5 3.0 signal information this section provides information on the signal groups for the pentium iii processor mobile module featuring intel speedstep technology. the signals are defined for compatibility with future intel mobile modules. 3.1 signal definitions table 1 provides a list of signals by category and the corresponding number of signals in each category. for proper signal termination, please contact your intel field representative for further information. table 1. connector signal summary signal group number of pins memory 109 agp 60 pci 58 processor/piix4e/m sideband 8 speedstep technology 4 power management 7 clocks 9 voltage: v_dc 20 voltage: v_3s 9 voltage: v_3 16 voltage: v_5 3 voltage: vccagp 4 voltage: v_cpupu 1 voltage: v_clk 1 itp/jtag 9 module id 4 ground 45 reserved 33 total 400
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 6 datasheet 243356-005 3.1.1 signal list the following notations are used to denote signal type: i input pin o output pin o d open-drain output pin requiring a pullup resistor i d open-drain input pin requiring a pullup resistor i/o d input/open-drain output pin requiring a pullup resistor i/o bi-directional input/output pin the signal description also includes the type of buffer used for a particular signal: gtl+ open-drain gtl+ interface signal pci pci bus interface signals agp agp bus interface signals cmos the cmos signals, depending on functional group, are 1.5v, 2.5v, or 3.3v.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 7 3.1.2 memory signal description table 2 provides descriptions of the memory interface signals. table 2. memory signal descriptions name type voltage description mecc[7:0] i/o cmos v_3 memory ecc data: these signals carry memory ecc data during access to dram. ecc is not supported on intel mobile modules. csa[5:o]# o cmos v_3 chip select (sdram): these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. dqma[7:0] o cmos v_3 input/output data mask (sdram): these pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle. mab[9:0]# mab[10] mab[12:11]# mab[13] o cmos v_3 memory address (sdram): this is the row and column address for dram. the 82443bx host bridge system controller has two identical sets of address lines (maa and mab#). the mobile module supports only the mab set of address lines. for additional addressing features, please refer to the intel ? 440bx agpset: 82443bx host bridge/ controller datasheet (order number: 290633-001). mwea# o cmos v_3 memory write enable (sdram): mwea# should be used as the write enable for the memory data bus. srasa# o cmos v_3 sdram row address strobe (sdram): when active low, this signal latches row address on the positive edge of the clock. srasa# also allows row access and pre-charge. scasa# o cmos v_3 sdram column address strobe (sdram): when active low, this signal latches column address on the positive edge of the clock. scasa# also allows column access. cke[5:0] o cmos v_3 sdram clock enable (sdram): sdram clock enable pin. when these signals are deasserted, sdram enters power-down mode. each row is individually controlled by its own clock enable. md[63:0] o cmos v_3 memory data: these signals are connected to the dram data bus and, they are not terminated on the mobile module.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 8 datasheet 243356-005 3.1.3 agp signals table 3 provides descriptions of the agp interface signals. table 3. agp signal descriptions name type voltage description gad[31:0] i/o agp v_3 agp address/data : the standard agp address and data lines. this bus functions in the same way as the pci ad[31:0] bus. the address is driven with frame# assertion, and data is driven or received in following clocks. gc/be[3:0]# i/o agp v_3 agp command/byte enable: this bus carries the command information during agp cycles when pipe# is used. during an agp write, this bus contains byte enable information. the command is driven with frame# assertion, and byte enables corresponding to supplied or requested data are driven on the following clocks. gframe# i/o agp v_3 agp frame: this signal is not used during agp transactions and remains deasserted by an internal pullup resistor. assertion indicates the address phase of a pci transfer. negation indicates that the cycle initiator desires one more data transfer. gdevsel# i/o agp v_3 agp device select : this signal provides the same function as pci devsel#. it is not used during agp transactions. the 82443bx host bridge system controller drives this signal when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. girdy# i/o agp v_3 agp initiator ready : indicates the agp compliant target is ready to provide all write data for the current transaction. the signal is asserted when the initiator is ready for a data transfer. gtrdy# i/o agp v_3 agp target ready : this signal indicates the agp compliant master is ready to provide all write data for the current transaction. the signal is asserted when the target is ready for a data transfer. gstop# i/o agp v_3 agp stop: this signal provides the same function as pci stop#. it is not used during agp transactions. asserted by the target to request the master to stop the current transaction. greq# i agp v_3 agp request: agp master requests for agp. ggnt# o agp v_3 agp grant: this signal provides the same function as on pci. additional information is provided on the st[2:0] bus. pci grant: permission is given to the master to use pci. gpar i/o agp v_3 agp parity : a single parity bit is provided over gad[31:0] and gc/ be[3:0]. this signal is not used during agp transactions. pipe# i agp v_3 pipelined request: this signal is asserted by the current master to indicate a full width address that is to be queued by the target. the master queues one request each rising clock edge while pipe# is asserted. sba[7:0] i agp v_3 sideband address : this bus provides an additional conduit to pass address and commands to the 82443bx host bridge system controller from the agp master. rbf# i agp v_3 read buffer full : this signal indicates if the master is ready to accept previously requested, low-priority read data.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 9 st[2:0] o agp v_3 status bus: provides information from the arbiter to an agp master on what it may do. these bits only have meaning when ggnt is asserted. adstb[b:a] i/o agp v_3 ad bus strobes : provides timing for double-clocked data on the gad bus. the agent providing data drives these signals. these signals are identical copies of each other. sbstb i/o agp v_3 sideband strobe : provides timing for a sideband bus. the sba[7:0] (agp master) drives the sideband strobe. table 3. agp signal descriptions name type voltage description
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 10 datasheet 243356-005 3.1.4 pci signals table 4 provides descriptions of the pci signals. table 4. pci signal descriptions name type voltage description ad[31:0] i/o pci v_3 address/data: the standard pci address and data lines. the address is driven with frame# assertion, and data is driven or received in the following clocks. c/be[3:0] i/o pci v_3 command/byte enable: the command is driven with frame# assertion, and byte enables corresponding to supplied or requested data are driven on the following clocks. frame# i/o pci v_3 frame: assertion indicates the address phase of a pci transfer. negation indicates that the cycle initiator desires one more data transfer. devsel# i/o pci v_3 device select: the 82443bx host bridge drives this signal when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o pci v_3 initiator ready: asserted when the initiator is ready for a data transfer. trdy# i/o pci v_3 target ready: asserted when the target is ready for a data transfer. stop# i/o pci v_3 stop: asserted by the target to request the master to stop the current transaction. plock# i/o pci v_3 lock: indicates an exclusive bus operation and may require multiple transactions to complete. when lock# is asserted, nonexclusive transactions may proceed. the 82443bx supports lock for cpu initiated cycles only. pci initiated locked cycles are not supported. req[4:0]# i pci v_3 pci request: pci master requests for the pci. gnt[4:0]# o pci v_3 pci grant: permission is given to the master to use pci. phold# i pci v_3 pci hold: this signal comes from the expansion bridge. it is the bridge request for pci. the 82443bx host bridge will drain the dram write buffers, drain the processor-to-pci posting buffers, and acquire the host bus before granting the request via phlda#. this ensures that gat timing is met for isa masters. the phold# protocol has been modified to include support for passive release. phlda# o pci v_3 pci hold acknowledge: this signal is driven by the 82443bx host bridge to grant pci to the expansion bridge. the phlda# protocol has been modified to include support for passive release. par i/o pci v_3 parity: a single parity bit is provided over ad[31:0] and c/be[3:0]#.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 11 3.1.5 intel speedstep technology signals table 5 provides the intel speedstep technology signal descriptions. serr# i/o pci v_3 system error: the 82443bx asserts this signal to indicate an error condition. for further information, refer to the intel ? 440bx agpset: 82443bx host bridge/controller datasheet (order number: 290633- 001) . clkrun# i/o d pci v_3 clock run: an open-drain output and input. the 82443bx host bridge requests the central resource, piix4e/m, to start or maintain the pci clock by asserting clkrun#. the 82443bx host bridge tri- states clkrun# upon deassertion of reset (since clk is running upon deassertion of reset). pci_rst# i cmos v_3 reset: when asserted, this signal asynchronously resets the 82443bx host bridge. the pci signals also tri-state, compliant with pci revision 2.1 specifications . table 4. pci signal descriptions name type voltage description table 5. intel speedstep technology signal description name type voltage description g_lohi# i cmos v_3s speedstep state transition : generated by the system electronics, this signal defines a speedstep state change to the speedstep state machine. this signal must be high on the rising edge of vr_on. g_cpu_stp# i cmos v_3s speedstep cpu_stp# : the cpu_stp# signal must be gated on the system electronics by vrchgng# and then routed to g_cpu_stp# on the connector and to the clock generator. vrchgng# o d cmos v_3s voltage changing : a speedstep state machine signal that indicates that the actual state change is in progress ? the vr setpoint has changed and the vr is settling. when this signal deasserts, the new speedstep state will settle on the processor. the system electronics will use this signal to generate an sci to force a transition out of deep sleep. also used to gate cpu_stp# on the system electronics. g_sus_stat1# o cmos v_3 g_sus_stat1#: the system electronics uses this signal to gate sus_stat1# from the piix4e/m.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 12 datasheet 243356-005 3.1.6 processor and piix4e/m sideband signals table 6 provides descriptions of the processor and piix4e/m sideband signals. note: see table 9 for v_cpupu definition. table 6. processor and piix4e/m sideband signal descriptions name type voltage description ferr# o d cmos v_cpupu numeric coprocessor error: this pin functions as an ferr# signal supporting coprocessor errors. this signal is tied to the coprocessor error signal on the processor and is pulled active low by the processor to the piix4e/m. ignne# i d cmos v_cpupu ignore error: this open-drain signal is connected to the ignore error pin on the processor and is driven by the piix4e/m. init# i d cmos v_cpupu initialization: init# is asserted by the piix4e/m to the processor for system initialization. this signal is an open-drain. intr i d cmos v_cpupu processor interrupt: intr is driven by the piix4e/m to signal the processor that an interrupt request is pending and needs to be serviced. this signal is an open-drain. nmi i d cmos v_cpupu non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the piix4e/m isa bridge generates an nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. this signal is an open- drain. a20m# i d cmos v_cpupu address bit 20 mask: when enabled, this open-drain signal causes the processor to emulate the address wraparound at 1 mb, which occurs on the intel 8086 processor. smi# i d cmos v_cpupu system management interrupt: smi# is an active-low synchronous output from the piix4e/m that is asserted in response to one of many enabled hardware or software events. the smi# open-drain signal can be an asynchronous input to the processor. however, in this chipset smi# is synchronous to pclk. stpclk# i d cmos v_cpupu stop clock: stpclk# is an active-low, synchronous open-drain output from the piix4e/m that is asserted in response to one of many hardware or software events. stpclk# connects directly to the processor and is synchronous to pciclk. when the processor samples stpclk# asserted, the processor responds by entering a low-power state (quick start). the processor will only exit this mode when this signal is deasserted.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 13 3.1.7 power management signals table 7 provides descriptions of the power management signals. the sm_clk and sm_data signals refer to the two-wire serial smbus interface. although this interface is currently used solely for the digital thermal sensor, the smbus contains reserved serial addresses for future use. note: v_3always is a 3.3-v supply and is generated whenever v_dc is available and supplied to the piix4e/m resume well. table 7. power management signal descriptions name type voltage description sus_stat1# i cmos v_3always suspend status: this signal connects to the sus_stat1# output of the piix4e/m. sus_stat1# provides information on the host clock status and is asserted during all suspend states. vr_on i cmos v_3 vr_on: voltage regulator on. this 3.3-v (5.0-v tolerant) signal controls the operation of the voltage regulator. vr_on should be generated as a function of the piix4e/m susb# signal, which is used for controlling the ?suspend state b? voltage planes. this signal should be driven by a digital signal with a rise/fall time of less than or equal to 1 s. (v il,max =0.4v, v ih,min =3.0v.) vr_pwrgd o v_3 vr_pwrgd: this signal is driven high by the mobile module to indicate that the voltage regulator is stable and is pulled low using a 100-k resistor when inactive. it can be used in some combinations to generate the system pwrgood signal. bxpwrok i cmos v_3 power ok to bx: this signal must go active at least 1 ms after the v_3 power rail is stable and 1 ms prior to deassertion of pcirst#. sm_clk i/o d cmos v_3 serial clock: this clock signal is used on the smbus interface to the digital thermal sensor. sm_data i/o d cmos v_3 serial data: an open-drain data signal on the smbus interface to the digital thermal sensor. atf_int# o d cmos v_3 atf interrupt: an open-drain output signal of the digital thermal sensor.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 14 datasheet 243356-005 3.1.8 clock signals table 8 provides descriptions of the clock signals. table 8. clock signal descriptions name type voltage description pclk i pci v_3 pci clock in: pclk, an input to the mobile module, is one of the system?s pci clocks. this clock is used by all of the 82443bx host bridge logic in the pci clock domain. this clock is stopped when the piix4e/m pci_stp# signal is asserted "and/or" during all suspend states. hclk0 i cmos v_clk host clock in: this clock is an input to the mobile module from the ck100-m/ck100-sm clock source. the processor and the 82443bx host bridge system controller use hclk0. this clock is stopped when the piix4e/m cpu_stp# signal is asserted "and/or" during all suspend states. note : the signal names hclk0 and bclk are used interchangeably. hclk1 i cmos v_clk host clock in: this clock is an input to the mobile module from the ck100-m/ck100-sm clock source. hclk1 is not implemented on the mobile module. dclk0 o cmos v_3 sdram clock out: a 66-mhz sdram clock reference generated internally by the 82443bx host bridge system controller onboard pll. it feeds an external buffer that produces multiple copies for the so- dimms. dclkrd i cmos v_3 sdram read clock: a feedback reference from the sdram clock buffer. the 82443bx host bridge system controller uses this clock when reading data from the sdram array. dclkrd is not implemented on the mobile module. dclkwr i cmos v_3 sdram write clock: a feedback reference from the sdram clock buffer. the 82443bx host bridge system controller uses this clock when writing data to the sdram array. gclkin i cmos v_3 agp clock in: the gclkin input is a feedback reference from the gclko signal. gclko o cmos v_3 agp clock out: this signal is generated by the 82443bx host bridge system controller onboard pll from the hclk0 host clock reference. the frequency of gclko is 66 mhz. the gclko output is used to feed both the pll reference input pins on the 82443bx host bridge system controller and the agp device. the board layout must maintain complete symmetry on loading and trace geometry to minimize agp clock skew. fqs o cmos v_3s frequency select: this output indicates the desired host clock frequency for the mobile module.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 15 3.1.9 voltage signals table 9 provides descriptions of the voltage signals. table 9. voltage descriptions name type number of pins description v_dc i 20 dc input: 7.5v ~ 21.0v v_3s i 9 susb# controlled 3.3v: a power managed 3.3-v supply, and an output of the voltage regulator on the system electronics. this rail is off during str, std, and soff. v_5 i 3 susc# controlled 5.0v: a power managed 5.0-v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_3 i 16 susc# controlled 3.3v: a power managed 3.3-v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. vccagp i 4 agp i/o voltage : this voltage rail is not implemented on the mobile module and is defined for upgrade purposes only. intel recommends that this voltage rail be connected to v_3 on the system electronics. v_cpupu o 1 processor i/o ring: the mobile module drives v_cpupu to power the processor interface signals, such as the piix4e/m open- drain pullups for the processor/piix4e/m sideband signals. v_cpupu is tied to 3.3v for the mobile module. v_clk o 1 processor clock rail: the mobile module drives v_clk to power the ck100-m vddcpu rail.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 16 datasheet 243356-005 3.1.10 itp and jtag pins table 10 provides descriptions of the itp and jtag signals, which the system manufacturer can use to implement a jtag chain and an itp port if desired. note: fs_reset# and fs_prdy# are pulled up to vtt inside the mobile processor core. 3.1.11 miscellaneous pins table 11 provides descriptions of the miscellaneous signal pins. table 10. itp and jtag pins name type voltage description tdo o d v_cpupu jtag test data out: a serial output port. tap instructions and data are shifted out of the processor from this port. tdi i vtt jtag test data in: a serial input port. tap instructions and data are shifted into the processor from this port. tms i vtt jtag test mode select: this pin controls the tap controller change sequence. tclk i vtt jtag test clock: a testability clock for clocking the jtag boundary scan sequence. trst# i vtt jtag test reset: this signal asynchronously resets the tap controller in the processor. fs_preq# i vtt debug mode request: this signal is driven by the itp and makes a request to enter debug mode. fs_prdy# o vtt debug mode ready: this signal is driven by the processor and informs the itp that the processor is in debug mode. fs_reset# o vtt processor reset: the processor reset status to the itp. vtt o vtt gtl+ termination voltage: this pin is used by the poweron pin on the itp debug port to determine when the target system is on. the poweron pin is pulled up using a 1-k ? resistor to vtt. other itp signals might use this power rail for pullup. table 11. miscellaneous pin descriptions name type number description module id[3:0] o cmos 4 module revision id : these pins track the revision level of the mobile module. a 100-k pullup resistor to v_3s must be placed on the system electronics for these signals. see section 8.0 for more detail. ground i 45 ground reserved rsvd 33 unallocated reserved pins. all reserved pins must not be connected.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 17 3.2 connector pin assignments table 12 lists the signals for each pin of the connector to the system electronics. refer to section 3.3 for the pin assignments. table 12. connector pin assignment pin number row a row b row c row d row e 1 sba5 adstbb gnd gad31 sba7 2 gad25 gad24 sba6 sba4 sba0 3 gad30 gad29 gad26 gad27 gnd 4 gnd vccagp gad4 gad6 gda8 5 rbf# gad1 gad3 gad5 gc/be0# 6 bxpwrok reserved gad2 adstba gnd 7 md0 md1 v_3 clkrun# gad7 8 md2 md33 gnd md32 md34 9 md36 md4 md3 md35 md34 10 md7 md38 md37 md6 md5 11 md41 md42 md40 md39 md8 12 md43 md11 gnd md10 md9 13 md14 md45 md44 md13 md12 14 mecc4 mecc0 nd15 nd47 nd46 15 scasa# mwea# mecc5 reserved gnd 16 gnd mid1 dqma0 dqma1 reserved 17 v_3 dqma4 mid0 dqma5 csa# 18 csa1# csa2# csa4# csa3# gnd 19 srasa# csa5# mab0# mab1# reserved 20 reserved reserved mab2# reserved mab3# 21 reserved mab4# gnd reserved mab6# 22 reserved reserved mab5# reserved mab7# 23 mab8# reserved reserved msb9# mab10 24 reserved mab11# mab12# reserved dclk0 25 mab13 v_3 gnd cke0 dclkrd 26 cke1 mid2 cke3 ce4 gnd 27 cke5 cke2 mid3 c_cpu_stp# vrchgng# 28 reserved g_lo/hi# dqma2 dclkwr gnd 29 gnd vtt reserved fs_preq# dqma3 30 fs_reset# v_3 md26 gnd md25 31 fs_prdy# gnd md58 md57 md60 32 g_sus_stat1# smclk tdo tclk ferr# 33 reserved smdat tdi tms ignne#
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 18 datasheet 243356-005 34 reserved fqs reserved trst# atf_int# 35 reserved v_5 v_3s v_3s v_3s 36 v_cpupu v_5 v_3s v_3s v_3s 37 v_clk v_5 v_3s v_3s v_3s 38 reserved reserved reserved reserved reserved 39 v_dc v_dc v_dc v_dc v_dc 40 v_dc v_dc v_dc v_dc v_dc table 12. connector pin assignment pin number row a row b row c row d row e pin number row f row g row h row j row k 1 greq# gnd pip# sba3 gnd 2 st0 st1 sba1 sbstb gclki 3 ggnt# st2 sba2 gnd cglk0 4 gad13 gstop# gad16 gad20 gad23 5 gad12 gpar gad18 gad17 gc/be3# 6 gad10 gad15 gframe# gnd gad22 7 gad11 gc/be1# gtrdy# gc/be2# gad21 8 gad9 gad14 gdevesel# girdy# gad19 9 gnd vccagp gnd vccagp gad28 10 ad0 ad4 ad2 ad3 ad1 11 gnd c/be0# ad6 gnd ad5 12 vccagp ad10 ad7 ad8 ad9 13 mecc1 ad13 gnd ad12 ad11 14 serr# par ad15 c/be1# ad14 15 ad16 trdy# stop# devsel# plock# 16 ad19 gnd ad17 gnd ad18 17 ad23 ad30 ad24 c/be2# ad21 18 ad27 ad22 c/be3# ad26 pclk 19 pci_rst# gnd ad20 ad28 gnd 20 reserved phold# ad31 ad29 ad25 21 irdy# frame# gnd req1# req0# 22 gnd gnt2# req2# req3# gnt3# 23 gnt1# gnt4# gnt0# req4# gnd 24 gnd phlda# gnd v_3 md59 25 dqma6 mecc7 md50 md51 md54 26 mecc2 md48 md18 md52 md24
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 19 3.3 pin and pad assignments the 400-pin mmc-2 connector has a 1.27-mm pitch and a bga style surface mount. refer to section 6.1.3 for size information. figure 2 shows the mmc-2 connector pad assignments. 27 dqma7 md16 md19 gnd md23 28 mecc6 md17 md21 md53 md55 29 mecc3 md49 md20 md22 md56 30 md27 md28 gnd md62 md63 31 gnd md29 md61 md30 md31 32 dmi# intr vr_on gnd gnd 33 nmi sus_stat1# vr_pwrgd gnd hclk0 34 a20m# stpclk# init# gnd gnd 35 v_3 v_3 v_3 gnd hclk1 36 v_3 v_3 v_3 gnd gnd 37 v_3 v_3 v_3 v_3 v_3 38 reserved reserved reserved reserved reserved 39 v_dc v_dc v_dc v_dc v_dc 40 v_dc v_dc v_dc v_dc v_dc
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 20 datasheet 243356-005 figure 2. mmc-2 connector pad footprint table 13 summarizes some of the key connector specifications. !""#$%&'()&&*+,)-'.)),/-%&, 012'$34'566%7&8*&,6 !" 9 : 5 table 13. connector specifications parameter condition specification material contact copper alloy housing thermo-plastic molded compound: lcp electrical current 0.5a voltage 50 vac insulation resistance 100 m ? termination resistance 20-m ? maximum at 20-mv open circuit with 10 ma capacitance 5-pf maximum per contact mechanical mating cycles 50 cycles connector mating force 50-lbs (22.7 kg) maximum contact unmating force 30-lbs (13.6 kg) maximum
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 21 4.0 functional description 4.1 pentium iii processor mobile module featuring intel speedstep technology the pentium iii processor mobile module featuring intel speedstep technology runs at speeds of 750/600 mhz, 700/550 mhz, 650/500 mhz, and 600/500 mhz, and offers a 100-mhz psb. 4.2 l2 cache the on-die l2 cache has 256 kb, is eight-way set associative, and runs at the speed of the processor core. 4.3 the 82443bx host bridge system controller intel's 82443bx host bridge system controller is a highly integrated device that combines the bus controller, the dram controller, and the pci bus controller into one component. the 82443bx host bridge has multiple power management features designed specifically for notebook systems such as: clkrun#, a feature that enables controlling of the pci clock on or off. the 82443bx host bridge suspend modes, which include suspend-to-ram (str), suspend- to-disk (std), and power-on-suspend (pos). system management ram (smram) power management modes, which include compatible smram (c_smram) and extended smram (e_smram). c_smram is the traditional smram feature implemented in all intel pci chipsets. e_smram is a new feature that supports write-back cacheable smram space up to 1 mb. to minimize power consumption while the system is idle, the internal 82443bx host bridge clock is turned off (gated off) when there is no processor and pci activity. this is accomplished by setting the g_clk enable bit in the 82443bx power management register through the system bios. 4.3.1 memory organization the memory interface of the 82443bx host bridge is available at the connector. this allows for the following: one set of memory control signals, sufficient to support up to three so-dimm sockets and six banks of sdram at 100 mhz one cke signal for each bank memory features not supported by the 82443bx host bridge system controller in this product are: eight banks of memory 256-mb memory devices second set of memory address lines (maa[13:0])
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 22 datasheet 243356-005 extended data out (edo) dram 66-mhz memory bus the clocking architecture supports the use of sdram. due to tight timing requirements of the 100-mhz sdram clocks, the clocking mode for sdram memory configurations allows all host and sdram clocks to be generated from the same clocking architecture on the system electronics. for complete details about memory device support, organization, size, and addressing when using sdram memory and trace length guidelines, refer to the intel? pentium? iii processor mobile module system electronics 100-mhz layout guidelines revision 1.0 (or-1780). 4.3.2 reset strap options several strap options on the memory address bus define the behavior of the mobile module after reset. other straps are allowed to override the default settings. table 14 shows the various straps and their implementation. 4.3.3 pci interface the pci interface of the 82443bx host bridge is available at the mmc-2 connector. the 82443bx host bridge supports the pci clockrun protocol for pci bus power management. in this protocol, pci devices assert the clkrun# open-drain signal when they require the use of the pci interface. refer to the pci mobile design guide for complete details on the pci clockrun protocol. the 82443bx host bridge is responsible for arbitrating the pci bus. the 82443bx host bridge can support up to five pci bus masters. there are five pci request/grant pairs (req[4:0]# and gnt[4:0]#) available on the connector. note: the pci interface on the mmc-2 connector is 3.3v only. pci devices that are 5.0v are not supported. the 82443bx host bridge system controller is compliant with the pci 2.1 specification , which improves the worst case pci bus access latency from earlier pci specifications. the 82443bx host bridge supports only mechanism #1 for accessing pci configuration space. this implies that signals ad[31:11] are available for pci idsel signals. however, since the 82443bx host bridge table 14. configuration straps for the 82443bx host bridge system controller signal function module default setting optional override on system electronics mab[12]# host frequency select strapped high on the module for 100 mhz none mab[11]# in order queue depth no strap, maximum queue depth is set at 8 none mab[10]# quick start select strapped high on the module for quick start mode none mab[9]# agp disable no strap (agp is enabled) strap high to disable agp mab[7]# mm configuration no strap (standard mmc-2 mode) none mab[6]# host bus buffer mode select strapped high on the mobile module for mobile psb buffers none
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 23 is always device #0, ad11 will never be asserted during pci configuration cycles as an idsel. the 82443bx reserves ad12 for the agpbus. thus, ad13 is the first available address line usable as an idsel. intel recommends that ad18 be used by the piix4e/m. 4.3.4 agp interface the 82443bx host bridge system controller is compliant with the agp interface specification revision 2.0 , which supports an asynchronous agp interface coupling to the 82443bx core frequency. the agp interface can achieve real data throughput in excess of 500 mb per second using an agp 2x graphics device. actual bandwidth may vary depending on specific hardware and software implementations. 4.4 intel speedstep technology intel speedstep technology allows the processor to switch between two core frequencies without resetting the processor or changing the system bus frequency. the processor has two bus ratios programmed instead of one. a lower frequency mode maximizes battery life, and a higher frequency mode provides processor performance similar to desktop pentium iii processor systems. the high performance mode should be used when the system is connected to an external power source because this mode requires more power. more cooling may be required as well. for example, it may be necessary to switch from passive to active cooling when using the high performance mode. for more detailed technical information regarding intel speedstep technology, refer to the geyserville hardware technical specification rev. 2.0 (or-1728) and the geyserville software architecture specification rev 1.5 (sc-2364). 4.5 power management 4.5.1 clock control architecture the clock control architecture has been optimized for notebook designs. the clock control architecture consists of seven different clock states: normal, stop grant, auto halt, quick start, halt/grant snoop, sleep, and deep sleep. the auto halt state provides a low-power clock state that can be controlled through the software execution of the hlt instruction. the quick start state provides a very low-power, low-exit latency clock state that can be used for hardware controlled "idle" states. the deep sleep state provides an extremely low-power state that can be used for power-on-suspend states, which is an alternative to shutting off the processor's power. the exit latency of the deep sleep state is 30 s. the stop grant state and the quick start clock states are mutually exclusive. for example, a strapping option on signal a15# chooses which state is entered when the stpclk# signal is asserted. strapping the a15# signal to ground at reset enables the quick start state. otherwise, asserting the stpclk# signal puts the processor into the stop grant state. table 15 provides information on the clock control states, and figure 3 illustrates the clock control architecture. performing state transitions not shown in figure 3 are neither recommended nor supported.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 24 datasheet 243356-005 table 15. clock state characteristics notes: 1. intel mobile modules do not support the sleep and stop grant states. 2. these values are not 100% tested and are specified at 50 c by design and characterization. 3. this value is not 100% tested and is specified at 35 c by design and characterization. 4. specifications labeled n/a are not available. clock state exit latency snooping system uses notes normal n/a yes normal program execution note 4 auto halt approximately 10 bus clocks yes software controlled entry- idle mode note 2 stop grant 10 bus clocks yes hardware controlled entry/exit mobile throttling notes 1,4 quick start through snoop , to halt/grant snoop state: immediate through stpclk# , to normal state: 10 bus clocks yes hardware controlled entry/exit mobile throttling note 2 halt/grant snoop a few bus clocks after the end of snoop activity yes supports snooping in the low-power states note 4 sleep to stop grant state 10 bus clocks no hardware controlled entry/exit desktop idle mode support notes 1,4 deep sleep 30 sno hardware controlled entry/exit mobile pos support note 3
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 25 figure 3. clock control states 4.5.1.1 normal state the normal state is the normal operating mode where the processor's core clock is running, and the processor is actively executing instructions. 4.5.1.2 auto halt state this is a low-power mode entered by the processor through the execution of the hlt instruction. the power level of this mode is similar to the stop grant state. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush#, or smi#). halt/grant snoop normal state hs=false stop grant auto halt hs=true quick start sleep deep sleep (!stpclk# and !hs) or stop break stpclk# and !qse and sga snoop occurs snoop serviced stpclk# and qse and sga (!stpclk# and !hs) or reset# snoop serviced snoop occurs !stpclk# and hs stpclk# and !qse and sga hlt and halt bus cycle halt break snoop serviced snoop occurs stpclk# and qse and sga !stpclk# and hs !slp# or reset# slp# bclk stopped bclk on and !qse bclk stopped bclk on and qse notes: halt break ? a20m#, binit#, flush#, init#, intr, nmi, preq#, reset#, smi# hlt ? hlt instruction executed hs ? processor halt state qse ? quick start state enabled sga ? stop grant acknowledge bus cycle issued stop break ? binit#, flush#, reset# intel mobile modules do not support shaded clock control states
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 26 datasheet 243356-005 asserting the stpclk# signal while in the auto halt state will cause the processor to transition to the stop grant state or the quick start state, where a stop grant acknowledge bus cycle will be issued. deasserting stpclk# will cause the processor to return to the auto halt state without issuing a new halt bus cycle. the smi# (system management interrupt) is recognized in the auto halt state. the return from the smi handler can be to either the normal state or the auto halt state. see the intel? architecture software developer's manual, volume iii: system programmer's guide for more information. no halt bus cycle is issued when returning to the auto halt state from system management mode (smm). the flush# signal is serviced in the auto halt state. after flushing the on-chip, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# and preq# signals are recognized while in the auto halt state. 4.5.1.3 stop grant state intel mobile modules do not support the stop grant state. in desktop systems, the processor enters this mode with the assertion of the stpclk# signal when it is configured for the stop grant state (via the a15# strapping option). the processor is still able to respond to snoop requests and latch interrupts. latched interrupts will be serviced when the processor returns to the normal state. only one occurrence of each interrupt event will be latched. a transition back to the normal state can be made by the deassertion of the stpclk# signal, or the occurrence of a stop break event (a binit#, flush#, or reset# assertion). the processor will return to the stop grant state after the completion of a binit# bus initialization unless stpclk# has been deasserted. reset# assertion will cause the processor to immediately initialize itself. however, the processor will stay in the stop grant state after initialization until stpclk# is deasserted. if the flush# signal is asserted, the processor will flush the on-chip caches and return to the stop grant state. a transition to the sleep state can be made by the assertion of the slp# signal. while in the stop grant state, assertions of smi#, init#, intr, and nmi (or lint[1:0]) will be latched by the processor. these latched events will not be serviced until the processor returns to the normal state. only one of each event will be recognized upon return to the normal state. 4.5.1.4 quick start state the processor enters this mode with the assertion of the stpclk# signal when the processor is configured for the quick start state (via the a15# strapping option). in the quick start state the processor is only capable of acting on snoop transactions generated by the psb priority device. because of its snooping behavior, quick start can only be used in single processor configurations. a transition to the deep sleep state can be made by stopping the clock input to the processor. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state, the processor is limited in its ability to respond to input. it is incapable of latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to flush# and binit# assertions. in the quick start state, the processor will not respond properly to any input signal other than stpclk#, reset#, or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 27 reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. 4.5.1.5 halt/grant snoop state the processor will respond to snoop transactions on the psb while in the auto halt, stop grant, or quick start state. when a snoop transaction is presented on the system bus, the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop has been serviced and the psb is quiet. after the snoop has been serviced, the processor will return to its previous state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state (except for those signal transitions that are required to perform the snoop). 4.5.1.6 sleep state intel mobile modules do not support the sleep state. in desktop systems, the sleep state is a very low-power state in which the processor maintains its context and the phase locked loop (pll) maintains phase lock. the sleep state can only be entered from the stop grant state. after entering the stop grant state the slp# signal can be asserted, causing the processor to enter the sleep state. the slp# signal is not recognized in the normal state or the auto halt state. the processor can be reset by the reset# signal while in the sleep state. if reset# is driven active while the processor is in the sleep state, then slp# and stpclk# must immediately be driven inactive to ensure that the processor correctly initializes itself. input signals (other than reset#) may not change while the processor is in or transitioning into or out of the sleep state. input signal changes at these times will cause unpredictable behavior. thus, the processor is incapable of snooping or latching any events in the sleep state. while in the sleep state the processor can enter its lowest power state, the deep sleep state. removing the processor's input clock puts the processor in the deep sleep state. picclk may be removed in the sleep state. 4.5.1.7 deep sleep state the deep sleep state is the lowest power mode the processor can enter while maintaining its context. the processor enters the deep sleep state by stopping the bclk input while the processor is in the sleep state or the quick start state. for proper operation, the bclk input should be stopped in the low state. the processor will return to the sleep state or the quick start state from the deep sleep state when the bclk input is restarted. due to the pll lock latency, there is a 30.0- s delay after the clocks have started before this state transition happens. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk turns on while transitioning out of the deep sleep state. the input signal restrictions for the deep sleep state are the same as for the sleep state, except that reset# assertion will result in unpredictable behavior.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 28 datasheet 243356-005 4.6 power consumption in power management modes the power data is divided by each power rail. each power rail is supplied to the mobile module through the mmc-2 connector. the total power values are based on typical power consumption. the data is captured at t amb = 25 c, t ttp = 25 c, and v_dc = 18.0v. note: all power consumption values are not 100% tested and have been characterized by design. table 16 , table 17 , and table 18 provide the module power consumption values in various power management modes. because mobile modules with the same frequencies may have different printed circuit board (pcb) revisions and different cpu steppings, refer to the product tracking code (ptc) lists before each table below to match the correct power consumption information with the correct mobile module. table 16 applies to mobile modules with the following ptcs. pmm65002001aa pmm60002001aa table 16. power consumption values i note: these power values should be used as power supply guidelines for power management modes. they have some guardband added for design margin. therefore, the total power does not necessarily add up as the sum of each power rail. "total power" is the sum of the individual "raw" power requirements with guardband added. state v_dc v_5 v_3 v_3s total power 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v auto halt 2.19w 1.36w 0.08w 0.06w 2.27w 2.16w 0.57w 0.41w 4.17w 3.50w quick start 1.77w 1.06w 0.08w 0.07w 2.04w 1.89w 0.62w 0.43w 3.43w 2.99w deep sleep 1.29w 0.82w 0.08w 0.08w 0.24w 0.24w 0.45w 0.29w 1.35w 1.05w str 0.04w 0.01w 0.01w 0.00w 0.05w
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 29 table 17 applies to mobile modules with the following ptcs. pmm70002101aa pmm65002101aa pmm60002101aa table 17. power consumption values ii note: these power values should be used as power supply guidelines for power management modes. they have some guardband added for design margin. therefore, the total power does not necessarily add up as the sum of each power rail. "total power" is the sum of the individual "raw" power requirements with guardband added. table 18 applies to mobile modules with the following ptcs. pmm75002101aa table 18. power consumption values iii note: these power values should be used as power supply guidelines for power management modes. they have some guardband added for design margin. therefore, the total power does not necessarily add up as the sum of each power rail. "total power" is the sum of the individual "raw" power requirements with guardband added. state v_dc v_5 v_3 v_3s total power 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v auto halt 2.56w 1.94w 0.06w 0.06w 2.31w 2.29w 0.03w 0.01w 4.93w 4.22w quick start 2.10w 1.72w 0.06w 0.06w 2.00w 2.00w 0.03w 0.04w 4.13w 3.74w deep sleep 1.64w 1.47w 0.05w 0.06w 0.26w 0.26w 0.04w 0.04w 1.96w 1.79w str 0.03w 0.01w 0.02w 0.00w 0.05w state v_dc v_5 v_3 v_3s total power 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v auto halt 2.92w 2.04w 0.24w 0.22w 2.21w 2.22w 0.03w 0.02w 5.18w 4.29w quick start 3.12w 1.75w 0.24w 0.22w 1.98w 2.00w 0.04w 0.04w 5.20w 3.75w deep sleep 1.74w 1.29w 0.29w 0.25w 0.27w 0.26w 0.03w 0.04w 2.25w 1.76w str 0.03 0.00 0.01 0.00 0.04
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 30 datasheet 243356-005 5.0 electrical specifications the following section provides the electrical specifications for the pentium iii processor mobile module featuring intel speedstep technology. 5.1 system bus clock signal quality specifications the hclk0 and bclk signal names are used interchangeably. 5.1.1 bclk dc specifications note: v ilx,min and v ih,max only apply when bclk is stopped. bclk should be stopped in the low state. see table 20 for the bclk voltage range specifications when bclk is running. 5.1.2 bclk ac specifications notes: 1. all ac timings for gtl+ and cmos signals are referenced to the bclk rising edge at 1.25v. all cmos signals are referenced at 0.75v. 2. the internal core clock frequency is derived from the psb clock. the psb clock to core clock ratio is determined during initialization and is predetermined by the intel mobile module. the bclk period allows a +0.5 ns tolerance for clock driver variation. 3. this value is measured on the rising edge of adjacent bclks at 1.25v. the jitter present must be accounted for as a component of bclk skew between devices. 4. the clock driver's closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the -20 db attenuation point, as measured into a 10-pf to a 2-pf load, should be less than 500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. see the ck97 clock synthesizer/driver specification (or-1089) for further details. 5. these values are not 100% tested and are specified by design characterization as a clock driver requirement. 6. specifications labeled n/a are not available. table 19. bclk dc specifications symbol parameter min max unit v il,bclk input low voltage, bclk - 0.3 0.5 v v ih,bclk input high voltage, bclk 2.0 2.625 v table 20. bclk ac specifications at the processor core pins t# parameter min nom max unit note system bus frequency n/a 100.0 n/a mhz notes 5, 6 bclk period n/a 10.0 n/a ns notes 2, 5, 6 bclk period stability n/a n/a 250 ps notes 3, 4, 5, 6 t3: bclk high time 2.85 n/a n/a ns at > 1.7v, notes 5, 6 t4: bclk low time 2.55 n/a n/a ns at > 0.7v, notes 5, 6 t5: bclk rise time 0.175 n/a 0.875 ns 0.9v ~ 1.6v, notes 5, 6 t6: bclk fall time 0.175 n/a 0.875 ns 1.6v ~ 0.9v, notes 5, 6
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 31 table 21 describes the signal quality specifications at the processor core for the psb clock (bclk) signal. figure 4 describes the signal quality waveforms for the psb clock at the processor core pins for proper signal termination, refer to the ?clocking guidelines? section in the mobile pentium ? iii processor/440bx agpset recommended design and debug practices (rddp-a) 100 mhz rev. 2.0 (sc-2760). notes: 1. on the rising edge of bclk, there must be a minimum overshoot to 2.0v. the clock must rise monotonically between v il,bclk and 2.0v and fall monotonically between v ih,bclk and v il,bclk . 2. these specifications apply only when bclk is running. see table 19 for the dc specifications when bclk is stopped. bclk may not be above v ih,bclk,max or below v il,bclk,min for more than 50% of the clock cycle. 3. the rising edge ringback voltage is the minimum absolute voltage that the bclk signal can dip back to after passing the v ih,bclk,min voltage limits. the falling edge ringback voltage is the maximum absolute voltage that the bclk signal can dip back to after passing the v il,bclk,max voltage limits. 4. specifications labeled n/a are not available. figure 4. bclk waveform at the processor core pins table 21. bclk signal quality ac specifications at the processor core t# parameter min max unit notes v1 v il,bclk -0.3 0.7 v notes 1, 4 v2 v ih,bclk 1.7 2.625 v notes 1, 4 v3 v in absolute voltage range -0.7 3.5 v undershoot, overshoot, note 2 v4 rising edge ringback 1.7 n/a v absolute value, notes 3, 4 v5 falling edge ringback n/a 0.7 v absolute value, notes 3, 4 bclk rising/falling slew rate 0.8 4.0 v/ns v1 max v3 max v2 min v4 v3 min v5 v0012-00 t3 t6 t4 t5
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 32 datasheet 243356-005 5.2 system power requirements table 22 provides the dc power supply design criteria. notes: 1. v_dc is set for 12.0v in order to determine typical v_dc current. 2. v_dc is set for 7.5v in order to determine maximum v_dc current. 3. a 20- s duration. 4. this is v_dc dependent. see figure 8 for data of idc-rms vs. v_dc. 5. these values are system dependent. 6. specifications labeled n/a are not applicable. 5.3 processor core voltage regulation the dc voltage regulator (dc/dc converter) is designed to support the core voltage and i/o ring voltage for current and future intel mobile processors. the dc voltage regulator provides the appropriate mobile processor core voltage, the gtl+ bus termination voltage, the processor sideband signal pull-up voltage, and the clock driver buffer voltage. of these voltages, only the processor sideband pullup voltage (v_cpupu) and the clock driver buffer voltage (v_clk) are delivered to the system electronics. the mobile module supports an input dc voltage range of 7.5v ~ 21.0v from the system battery or power supply. table 22. system power requirements symbol parameter min nom max unit notes v dc dc input voltage 7.5 12.0 21.0 v i dc dc input current 0.1 2.6 5.0 a notes 1,2 i dc_rms rms ripple current n/a n/a 7.5 a notes 4,6 i dc_surge maximum surge current for v dc n/a n/a 20.0 a notes 3,6 v 5 power managed 5.0-v supply 4.75 5.0 5.25 v i 5 power managed 5.0-v current, operating 20.0 50.0 100.0 ma i 5_surge maximum surge current for v 5 n/a n/a 1.5 a notes 3,6 v 3 power managed 3.3-v supply 3.135 3.3 3.465 v i 3 power managed 3.3-v current 0.8 1.2 3.0 a i 3_surge maximum surge current for v 3 n/a n/a 4.0 a notes 3,6 v cpupu processor i/o ring voltage 3.135 3.3 3.465 v i cpupu processor i/o ring current 0.0 10.0 20.0 ma v clk processor clock rail voltage 2.375 2.5 2.625 v i clk processor clock rail current 24.0 35.0 80.0 ma note 5
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 33 5.3.1 voltage regulator efficiency there are three voltage regulators on the mobile module. the voltage regulators generate the cpu core voltage and the cpu i/o ring voltage. the core voltage regulator provides the required current from the v_dc supply. intel speedstep technology and single frequency vcore efficiencies are shown in table 23 and table 24 . figure 5 and figure 6 provide charts of the efficiency values. the v_clk and vtt voltage regulators tap the v_3 plane. table 24. vcore power conversion efficiency at 1.35v table 23. vcore power conversion efficiency at 1.60v vcore = 1.60v icore (a) efficiency at v_dc + 7.50v efficiency at v_dc + 12.0v efficiency at v_dc + 21.0v 1 77% 71% 63% 2 85% 82% 78% 3 87% 85% 81% 4 87% 86% 82% 5 86% 86% 83% 6 85% 85% 83% 7 84% 84% 82% 8 83% 83% 81% 9 81% 82% 81% 10 80% 81% 80% 11 79% 80% 79% vcore = 1.35 icore (a) efficiency at v_dc + 7.50v efficiency at v_dc + 12.0v efficiency at v_dc + 21.0v 1 77.1% 70.8% 62.2% 2 84.4% 82.0% 76.8% 3 86.2% 84.5% 80.4% 4 85.7% 84.9% 81.0% 5 84.6% 84.3% 81.4% 6 83.2% 83.4% 80.9% 7 81.8% 82.2% 80.4% 8 80.3% 81.1% 79.5% 9 78.8% 79.9% 78.7%
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 34 datasheet 243356-005 figure 5. vr efficiency chart for vcore at 1.60v figure 6. vr efficiency chart for vcore at 1.35v vr efficiency at vcore = 1.60v 60% 62% 64% 66% 68% 70% 72% 74% 76% 78% 80% 82% 84% 86% 88% 90% 1234567891011 icore(a) efficiency(% ) v_dc = 7.5v v_dc = 12v v_dc = 21v vr efficiency for vcore = 1.35v 60% 62% 64% 66% 68% 70% 72% 74% 76% 78% 80% 82% 84% 86% 88% 90% 123456789 icore(a) efficiency(% ) v_dc = 7.5v v_dc = 12v v_dc = 21v
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 35 5.3.2 voltage regulator control the vr_on pin on the connector allows a 3.3-v signal to control the voltage regulator. the system manufacturer can use this signal to turn the voltage regulator on or off. vr_on should be controlled as a function of the same signal (susb#) used to control the system's switched 5.0-v and 3.3-v power planes. the piix4e/m defines suspend b as the power management state in which power is physically removed from the processor and the voltage regulator. in this state, the susb# pin on the piix4e/m controls these power planes. the mobile module provides the vr_pwrgd signal, which indicates that the voltage regulator power is operating at a stable voltage level. the system manufacturer should use this signal on the system electronics to control power inputs and to gate pwrok to the piix4e/m south bridge. table 25 provides the detailed definitions and sequences of the voltage signals. the following list includes additional specifications and clarifications of the power sequence timing and figure 7 provides an illustration. 1. the vr_on signal may only be asserted to a logical high by a digital signal after v_dc 7.5v, v_5 4.5v, and v_3 3.0v. 2. the rise time and fall time of vr_on must be less than or equal to 1.0 s. table 25. voltage signal definitions and sequences signal source definitions and sequences v_dc system electronics v_dc is required to be between 7.5v and 21.0v dc, and it is driven by the system electronics' power supply. v_dc powers the mobile module dc-to-dc converter for the processor core and i/o voltages. the mobile module cannot be hot inserted or removed while v_dc is powered on. v_5 system electronics the system electronics supplies v_5 for the voltage regulator. v_3 system electronics the system electronics supplies v_3 for the 82443bx and powers the mobile module's linear regulators for generating the v_clk and v_cpupu voltage rails. v_3 stays on during suspend. v_3s system electronics the system electronics supplies v_3s and is shut off during suspend. vr_on system electronics vr_on is a 3.3-v signal that enables the voltage regulator circuit. when driven active high the voltage regulator circuit is activated. the signal driving vr_on should be a digital signal with a rise/fall time of less than or equal to 1.0 s. (v il,max = 0.4v, v ih,min = 3.0v.) v_core module a result of vr_on being asserted, v_core is an output of the dc- dc regulator on the mobile module and is driven to the core voltage of the processor. vr_pwrgd module upon sampling the voltage level of v_core (minus tolerances for ripple), vr_pwrgd is driven active high. if vr_pwrgd is not sampled active within 1 second of the assertion of vr_on, then the system electronics should deassert vr_on. after v_core is stabilized, vr_pwrgd will assert to logic high (3.3v). this signal must not be pulled up by the system electronics. vr_pwrgd should be "logically anded" with v_3s to generate the piix4e/m input signal, pwrok. the system electronics should monitor vr_pwrgd to verify that it is asserted high prior to the active high assertion of piix4e/m pwrok. v_cpupu module v_cpupu is 3.3v. the system electronics uses this voltage to power the piix4e/m-to-processor interface circuitry. v_clk module v_clk is 2.5v. the system electronics uses this voltage to power the hclk[0:1] drivers for the processor clock.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 36 datasheet 243356-005 3. vr_on has its v ilmax = + 0.4v and v ihmin = +3.0v. 4. the vr_pwrgd will get asserted to logic high (3.3v) after v_core is stabilized and v_dc reaches 7.5v. this signal should not and can not be pulled up by the system electronics. 5. in the power-on process, intel recommends to raise the higher voltage power plane first (v_dc), followed by the lower power planes (v_5, v_3), and finally assert vr_on after above voltage levels are met on all rails. the power-off process should be the reverse, for example vr_on gets deasserted, followed by the lower power planes, and finally the higher power planes. 6. vr_on must monotonically rise through its v il to v ih and fall through its v ih to v il points. the sign of slope can not change between v il and v ih in rising and v ih and v il in falling. 7. vr_on must provide an instantaneous in-rush current to the mobile module with the values listed in table 26 . 8. vr_on valid-low time: this specifies how long vr_on needs to be low for a valid off before vr_on can be turned back on again. in going from a valid on to off and then back on, the following conditions must be met to prevent damage to the system or the mobile module: vr_on must be low for 1.0 ms. the original voltage level requirements for turn-on must be met before assertion of vr_on (i.e. v_dc 7.5v, v_5 4.5v, and v_3 3.0v). table 26. vr_on in-rush current instantaneous dc operating maximum 41.0 ma 0.1 a typical 0.2 ma 0.0 a
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 37 figure 7. power sequence timing 5.3.3 power planes: bulk capacitance requirements the placement of sufficient bulk capacitance on the system electronics board is critical to the operation of the mobile module and to ensure that the system design can accommodate future high frequency modules. intel has provided the maximum possible bulk capacitance on the mobile module. however, in order to achieve proper filtering and in-rush current protection, it is imperative that additional filtering be provided on the system electronics board. table 27 details the bulk capacitance requirements for the system electronics. note: observe the voltage rating requirement for the capacitors on each respective voltage rail. notes: 1. pw rok on i/o board should be active on when vr_pw rgd is active and v_3s is good. 2. cpu_rst from i/o board should be active for a minimum of 6.0 ms after pw rok is active and pll_stp# and cpu_stp# are inactive . note that pll_stp# is an and condition of rsmrst# and susb# on the piix4e/m. 3. this is the 5.0-v power supplied to the mmc-2 connector. this should be the first 5.0-v plane to power up. stays on during suspend. 4. g_lo/hi# must be high at the rising edge of vr_on. if it is not, the bios must assert this signal very early in core execut ion. 5. v_dc >= 7.5v, v_5>= 4.5v, v_3s>= 3.0v. 6. vr_pw rgd is specified active by the module regulator within less than or equal to 6.0-ms maximum after the assertion of vr_ on. 7. v_cpupu and v_clk are generated on the mobile module. v_cpupu v_clk note 7 note 7 vr_pw rgd v_dc v_3 v_5 v_3s vr_on g_lo/hi# note 5 0 ms min note 3 0 ms min note 4 note 6 0 ms min
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 38 datasheet 243356-005 table 27. bulk capacitance requirements per power plane notes: 1. placement of the above capacitance requirements should be located near the connector. 2. v_clk filtering should be located next to the system clock synthesizer. 3. rms ripple current specification depends on v_dc input for the module. see figure 8 . 4. if tantalum* capacitors are used, a 50% voltage derating practice must be observed. for example, a 5.0-v rail requires a 10.0-v rated capacitor. 5. in order to reduce esr, intel recommends the use of multiple bulk capacitors rather than a single large capacitor. 6. intel strongly recommends that system designers pay close attention to capacitor design recommendations. specifically, the "capacitance vs. temperature de-rating curve," "capacitance vs. applied dc voltage de- rating curve," and the "capacitance vs. frequency de-rating curve." some capacitor dielectrics are particularly susceptible to these conditions, for example y5v ceramic capacitors. 7. specifications labeled n/a are not available. figure 8 shows the dependence of v_dc ripple current on v_dc. power plane bulk capacitance requirements high frequency capacitance requirements notes total capacitance esr max rms ripple current v_dc 100.0 f 20.0 m ? 3.0a~ 5.0a 0.1 f, 0.01 f notes 1,3,4,5,6 v_5 100.0 f 100.0 m ? 1.0a 0.1 f, 0.01 f notes 1,4,5,6 v_3 470.0 f 100.0 m ? 1.0a 0.1 f, 0.01 f notes 1,4,5,6 v_3s 100.0 f 100.0 m ? n/a 0.1 f, 0.01 f notes 1,4,5,6 vcc_agp 22.0 f 100.0 m ? 1.0a 0.1 f, 0.01 f notes 1,4,5,6 v_cpupu 2.2 f n/a n/a 8200.0 pf notes 1,5,6,7 v_clk 10.0 f n/a n/a 8200.0 pf notes 1,2,5,6,7
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 39 figure 8. v_dc rms ripple current 5.3.4 system power supply circuit protection 5.3.4.1 dc power system protection the recommended dc power system protection consists of the following: a dc power supply capable of delivering 7.5v to 21.0v to the mobile module an overcurrent protection circuit providing a means to limit the maximum current available to the system a slew rate control circuit providing a controlled voltage slew rate at turn on, which provides protection for components sensitive to fast voltage rise times an undervoltage lockout circuit that protects against potentially damaging high currents, which might be encountered if the dc power supply voltage is too low an overvoltage lockout circuit providing protection from potentially damaging high dc power supply voltages bulk decoupling capacitors providing filtering and a reservoir of energy, which can provide a faster transient response than the power supply v_dc input rms ripple current vs. v_dc voltage 7.39 7.13 6.85 6.57 6.31 6.08 5.86 5.67 5.49 5.33 5.17 5.04 4.91 4.79 4.68 4.57 4.47 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 7.00 7.50 8.00 7 8 9 101112131415161718192021 v_dc(v) input rms ripple current(a)
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 40 datasheet 243356-005 figure 9. v_dc power system protection block diagram 5.3.4.2 v_dc power supply the power supply must be able to deliver 7.5v to 21.0v to the mobile module, measured at the mobile module. 5.3.4.3 overcurrent protection the overcurrent protection circuit provides a way to limit current drawn by the mobile module. under normal operating conditions, i_dc should not be expected to exceed 3.0a at v_dc = 7.5v. to allow for component variations and margining issues, a reasonable i_dc current limit would be 6.0a. ;<=('$)>*- ?@//ab !"##$%&'(#$)*+ 0c*-+@--*&, $-),*+,%)& d?**'?*+,%)&'efgf!fgh i&4*-c)a,37* j)+k)@, !"##$"#,-./0$1232425+ 0c*-c)a,37* j)+k)@, d "##$"#,-./0$1232426+ ?a*>'l3,* ()&,-)a !"##$"#,-./0$1232421+ m@ak =*+)@/a%&7 (3/3+%,)-6 2)4@a*
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 41 figure 10. overcurrent protection circuit at the other end of the v_dc input range, the current will be somewhat less. at 14.0v, for example, the corresponding power could be produced with only 3.0a. in this example, a comparator, u1a, will be used to sense when v_dc is over 14.0v and will shift the current limit from 6.0a to 3.0a. let delimited)= 6.0a let i_dc(limit2)= 3.0a let b(q1)= 100 let r1= 5 m ? = 0.005 ? let r12= 100.0 ? let r13= 100.0 ? let v(r14) 1.8v let i(r20) 100.0 a let c36= 2.0k ?a*>'l3,*'()&,-)a 0c*-'(@--*&,'$-),*+,%)& r33 r36 r35 v_dc u1a c18 2.5v m3 2n7000 m1 si4435dy c9 v_dc v_dc u1b q1 2n2222a lm4040 + - power supply r2 r4 r16 r14 r12 r13 r20 r1 note : u1b must be able to operate with inputs near the v_dc rail. consider the lmc6762.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 42 datasheet 243356-005 figure 11. current shift model 5.3.4.4 current limit shift point comparator u1a should switch when the non-inverting input is equal to the 2.5-v reference on the inverting input, or when the voltage applied to v_dc is equal to the selected switch point and the voltage dropped across r36 is 2.5v. in this example, the change should occur when v_dc= 14.0v. equation 1. (the nearest standard 1% value is 9.01 k ? .) comparator u1a will pull its output low when v_dc falls below 14.0v, which will effectively put r33 in parallel with r14. when power is initially applied to the circuit, c18 charges up to 2.5v through r20. this slowly rising voltage is applied to the base of the current source, q1. the voltage on r14 is approximately 2.5v minus the base-emitter drop of about 0.7v (at 25c): v (r14) 1.8v. q1 is a 2n2222a with a moderate of about 100. therefore, the current through r13 is approximately equal to the current through r14. the charging of c18, provides a small increment of delay as u1 will not allow r4 to pull up the gate of m3 until q1 has pulled the non-inverting input of u1 down slightly. the voltage developed across r1 is a function of the load. equation 2. v(r1)= i_dc*r1 u1a +in v_dc r36 r35 r35 v_dc vref () vref r36 r35 14 2.5 () 2.5 2000
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 43 if the maximum i_dc expected is 3.0a, consider setting the i_dc current limit at 6.0a. if the current sense resistor, r1, is selected to be 5.0 m ? (0.005 ? ), the maximum voltage developed across this resistor can be calculated. consider now the case where v_dc is above 14.0v. equation 3. i_dc(limit)*rsense= 3.0a*5e-3= 15.0 mv) the offset voltage applied to the inverting input of the comparator, u1b, should then be 15.0 mv. if r13 is selected to be 100.0 ? , the current can then be calculated as shown in equation 4 below. equation 4. ioffset= 15.0 mv/100.0 ? = 150.0 a note: for a successful design, the input offset of the comparator should also be considered. one option is that the design offset is at least ten times greater than the device offsets. the value of r14 can now be calculated with equation 5 . equation 5. r14= 1.8v/150.0 a= 12.0 k ? (the nearest 1% value is 12.1k.) consider now the case when v_dc drops below 14.0v and the current limits shift to 6.0a. equation 6. i_dc(limit)*rsense= 6.0a*5e-3= 30.0 mv the offset voltage applied to the inverting input of the comparator, u1b, should then be 30.0 mv. if r13 is selected to be 100.0 ? , the current can then be calculated as shown in equation 7 below. equation 7. ioffset= 30.0 mv/100 ? = 300.0 a the value of the parallel combination of r14 and r33 can now be calculated as shown in equation 8 below. equation 8. rcombo= 1.8v/300.0 a= 6.0 k ? r14 is a 12.0-k resistor. if r33 is also 12.0k, the parallel combination will be 6.0k. in r20, the lm4040-2.5 has a very wide operating current range from 60.0 a to 15.0 a. in order to provide the current source base drive you will need equation 9 . equation 9. ibase ic/b= 300.0 a/100 = 3.0 a
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 44 datasheet 243356-005 if selected for i(r20), 100 a would be adequate for the reference and current source base drive. since both of these currents must be satisfied at the low power supply margin, a v_dc of 7.5v will be assumed. equation 10. r20 = (v_dc-vref)/i(r20) = 7.5-2.50)/100.0 a= 50.0 k ? (to allow for component tolerances, 51.0 k ? is recommended.) 5.3.4.5 slew rate control the slew rate control regulates the rate that the power supply voltage is applied to the system. let the threshold voltage of m1, v t = -1.0v let m1 v gs(sat) = -2.4v, also denoted as v sat let r16 = 100.0 k ? let t_delay = 500.0 s let c total = the sum or the bulk capacitors + the sum of the module capacitors = 5 x 22.0 f + 2 x 4.7 f= 119.4 f m1 is a low rds(on) p-channel mosfet such as the siliconix* si4435dy. when the power supply voltage is applied and increased to a value that exceeds the lockout value, (7.5v will be used in this example), the undervoltage lockout circuit, allows r4 to pull up the gate of m3 to start a turn-on sequence. m3 pulls its drain toward ground, forcing current to flow through r2. m1 will not start to source any current until after t_delay, with t_delay defined as shown in equation 11 and equation 12 below. equation 11. equation 12. the published minimum threshold of the si4435dy is a v gs of -1.0v, i.e. c9 must charge to 1.0v before m1 starts to turn on. the delay, t_delay, is the time required to charge c9 to 1.0v. assuming a negligible voltage drop across m3, when m3 is on, the voltage on the gate of m1, v g , with respect to ground, is the voltage developed across r2: vg v (r2) . if a minimum steady-state bias on m1 is desired to be -4.5v, this will be the voltage dropped across r16. at the low end of the v_dc margin, i.e. 7.5v, then v g can be derived from equation 13 below. equation 13. v g = v_dc+v gs = 7.5v- 4.5v = 3.0v (with respect to ground) t_delay r2 c9 . ln 1 vt v_dc vg . vgs r16 r16 r2 v_d c
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 45 equation 14. (the nearest standard 1% value is 66.5 k ? . the example will continue with r2= 66.5 k ? .) rearranging equation 8 to solve for c9 yields equation 15 . equation 15. now a value for c9 can be calculated. equation 16. c 9= 0.354 f (a close standard value of 0.33 f will yield a t_delay of 466.0 s.) the ramp-up time, t_ramp, is defined as shown in equation 17 . equation 17. if m1 has a vgs(sat) of -2.4v, then equation 18 applies. equation 18. t_ramp = 948.8 s the maximum current during the power-up ramp is shown in equation 19 below. equation 19. if the total capacitance, ctotal on the v_dc bus, is 119.4 f, then see equation 20 below. equation 20. imax = 0.944a from the values assumed and calculated, t_delay = 466.0 s, t_ramp = 949.0 s, and imax = 944.0 ma. r2 vg r16 . v_dc vg , r2 66.67 k ? = c9 t_delay r2 ln 1 vt v_dc vg . t_ramp r2 c9 . ln 1 vsat vgs . t_delay im a x c to ta l t v d d ctotal v_dc t_ramp .
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 46 datasheet 243356-005 5.3.4.6 undervoltage lockout the circuit below shows the undervoltage lockout portion of the v_dc supply circuit. this circuit protects and locks out the applied voltage to the mobile module to prevent an accidental turn-on at low v_dc supply voltages. warning: a low voltage applied to the mobile module could result in destructive current levels. figure 12. undervoltage lockout the output of the lm339 comparator is an open-collector and is low when the applied voltage at v_dc is less than 7.5v, which holds the gate of m3 low. consequently, the slew rate controller is not allowed to turn-on. the 2.5-v reference, v ref , voltage is derived from d7 in figure 10 . when a non-inverting input of the comparator exceeds v ref , 2.5v, the comparator trips and allows its output to go to a high z state. the gate of m3 can then be pulled up by r4, starting the controlled power-up slew. the model in figure 13 will be used to calculate the undervoltage lockout trip point. undervoltage lockout v_dc_a r4 m3 gate vref 2.5v v_dc v_dc lm339 r25 r18 r17 let v_dc_uvlock=7.5v let r17=10 k ? let r25=1 m ? let vcesat= 0.3v let vref=2.5v
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 47 figure 13. undervoltage lockout model vcesat is the saturation voltage of the comparator output transistor. the comparator trip point voltage can be calculated with equation 21 . equation 21. if power to the mobile module is to be held off until v_dc exceeds 7.5v, equation 21 can be rearranged to solve for r18. equation 22. a value for r18 can be determined by plugging these values into equation 23 . equation 23. r18 = 5.022 k ? (4.99 k ? is a standard 1% resistor value, which would provide lockout below 7.532v.) 5.3.4.7 overvoltage lockout the mobile module operates with a maximum input voltage of 21.0v. this circuit can be set to lock out the input voltage if it exceeds the desired input. undervoltage lockout model + vcesat 2.5v v_dc r25 r18 r17 v_dc_uvlock vref vref r18 vref vcesat r25 r17 r18 vref r17 . r25 . r25 v_dc_uvlock vref () . r17 vref vcesat () .
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 48 datasheet 243356-005 figure 14. overvoltage lockout the lm339 comparator is an open-collector output and is pulled low when the applied voltage at v_dc is too high, thus disabling the slew-rate circuit. the model in figure 15 below will be used for component calculations. figure 15. overvoltage lockout model assume that the desired v_dc overvoltage lockout is 21.0v. using equation 24 , the input to the non-inverting input of the ov lockout comparator can be calculated with the following equations. 0c*-c)a,37*'j)+k)@, m3 gate v_dc_a r4 2.5v v_dc v_dc lm339 r27 r23 r24 r26 v ref let r4=100 k ? let r24=100k let r26=1 m ? let r27=1 k ? overvoltage lockout model vinv r23 r24 v_dc vref vnoninv v_dc_a r27 r26 r4
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 49 equation 24. equation 25. vnoninv= 2.517v equation 26. the output of the ov lockout comparator will become active and pull down when the inverting input becomes greater than the 2.517v input on the non-inverting input. equation 26 can be rearranged to solve for r23. equation 27. the ov lockout comparator trip point is defined by vinv = vnoninv = 2.517v. equation 28 provides a solution for r23. equation 28. r23= 13.618 k ? (the nearest standard 1% value is 13.7 k ?. ) if v_dc exceeds 6.0v, the voltage on the ov lockout comparator inverting input will exceed 2.517v causing the comparator to trip, pulling its output low and disabling the power skew control circuit which, in turn, will disconnect v_dc from the mobile module. vnoninv vref r27 v_dc_ovlock vref () . r4 r26 r27 vinv v_dc_ovlockr23 . () r23 r24 r23 r24 vinv . v_dc_ovlock vinv
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 50 datasheet 243356-005 figure 16. recommended power supply protection circuit for the system electronics figure 17. simulation of v_dc voltage skew under voltage lockout over voltage lockout input bulk decoupling capacitors mmo processor module over current protection slew rate control 27uf 4.7uf 4.7uf 27uf 27uf 27uf 27uf 2.5v 2.5v v_dc v_dc v_dc v_dc lm339 lm339 m3 2n7000 si4435dy c9 v_dc v_dc v_dc v_dc lm339 2n2222a lm339 c18 lm4040 + - ac adaptor 0.3 1m 0.3 0.3 0.3 0.3 0.3 0.3 r25 r27 r23 r24 r26 r18 r17 r2 r4 r16 r14 r33 r12 r13 r36 r35 r20 r1 components values assumed and calculated r1 5m ? r20 20k ? , 5% r2 5.62k ? , 1% r23 71.5k ? , 1% r4 100k ? , 1% r24 100k ? , 1% r12 100 ? , 1% r25 1m, 5% r13 100 ? , 1% r26 1m, 5% r14 12.1k ? , 1% r27 1k ? , 1% r16 100k ? , 1% r33 12.1k ? , 1% r17 10k ? , 1% r35 9.1k ? , 1% r18 11k ? , 1% r36 2k ? , 1% c9 0.33 f c18 0.1 f
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 51 5.4 active thermal feedback 5.5 thermal sensor configuration register the configuration register of the thermal sensor controls the operating mode (auto convert vs. standby) of the device. since the processor temperature varies dynamically during normal operation, auto convert mode should be used exclusively to monitor processor temperature. table 29 shows the format of the configuration register. if the run/stop bit is low, then the thermal sensor enters auto convert mode. if the run/stop bit is set high, then the thermal sensor immediately stops converting and enters the standby mode. the thermal sensor will still perform temperature conversions in standby mode when it receives a one-shot command. however, the result of a one-shot command during auto convert mode is not guaranteed. intel does not recommend using the one-shot command to monitor temperature when the processor is active, only auto convert mode should be used. the thermal sensor can be configured in various interface modes for temperature sampling. intel recommends interfacing the thermal sensor using interrupt mode. for more detailed information regarding interface methods, please see the intel ? mobile module thermal diode temperature sensor application note available through your intel field representative . note: all reserved bits should be written as ?0? and read as ?don?t care? for programming purposes. table 28. thermal sensor smbus address function smbus address thermal sensor 1001 110 table 29. thermal sensor configuration register bit name reset state function 7 msb mask 0 masks smbalert# when high 6 run/stop 0 standby mode control bit. if it is low, then the device enters auto convert mode. if it is high, then the device immediately stops converting and enters standby mode where the one-shot command can be performed. 5-0 reserved 0 reserved for future use
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 52 datasheet 243356-005 6.0 mechanical specifications this section provides the physical dimensions for the pentium iii processor mobile module featuring intel speedstep technology. 6.1 mobile module dimensions figure 18 shows the mobile module board dimensions and the connector orientation. figure 18. board dimensions and mmc-2 connector orientation 6.1.1 pin 1 location of the mmc-2 connector figure 19 shows the location of pin 1 of the 400-pin connector. module mechanical x-y-z dimensions and thermal attach points unless otherwise specified: tolerances angles 0.5 .x 0.2 .xx 0.15 .xxx 0.075 * all dimensions are in mm
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 53 figure 19. board dimensions and mmc-2 connector?pin 1 orientation 6.1.2 printed circuit board figure 20 shows the minimum and maximum thickness of the printed circuit board (pcb). the range of pcb thickness allows for different pcb technologies to be used with current and future intel mobile modules. note: the system manufacturer must ensure that the mechanical restraining method and/or system-level emi contacts are able to support this range of pcb for compatibility with future intel mobile modules. figure 20. printed circuit board thickness min: 0.90 mm max: 1.10 mm printed circuit board
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 54 datasheet 243356-005 6.1.3 height restrictions figure 21 shows the height restrictions of the mobile module. the keep-out zone is also illustrated. three mating connectors are available in heights of approximately 4 mm, 6 mm, and 8 mm. the three sizes provide flexibility in choosing the system electronics components between the two boards. information on these connectors can be obtained from your intel field representative. figure 21. height restrictions 6.2 thermal transfer plate the ttps provide heat dissipation on the processor and the 82443bx, and they may vary on different generations of intel mobile modules. the ttps provide the thermal attach point where a system manufacturer can transfer heat through the notebook system using a heat pipe, a heat spreader plate, or a thermal solution. attachment dimensions for the thermal interface block to the ttps are provided in figure 22 , figure 23 , and figure 24 . the ttp on the mobile module is designed to be a high efficiency spreader. to fully take advantage of the mobile module thermal design and optimize the system thermal performance, the contact area (ac) needs to be a minimum of 30 mm x 30 mm. while it crucial to maximize the contact area, it is equally important to ensure that the contact area and/or the mobile module is free from warpage in an assembled configuration. warning: if warpage occurs, the thermal resistance of the mobile module could be adversely affected. when attaching a mating block to either of the ttps, intel recommends that a thermal elastomer should be used as an interface material. this material reduces the thermal resistance. the oem thermal interface block should be secured to the cpu ttp with m2 screws using a maximum torque of 1.5 kg*cm to 2.0 kg*cm (equivalent to 0.147 n*m to.197 n*m). the thread length of the m2 screws should be 2.25-mm gageable thread (2.25-mm minimum to 2.80-mm maximum). note 3 note 3 notes: 1. all values are nominal unless otherwise specified. 2. 3d cad model (pro/e native) available upon request. 3. these dimensions have changed.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 55 the mobile module is designed to ensure that the thermal resistance between the processor die center and a point directly above on the ttp surface is 0.35 c/w, under the following set of conditions. r ttp-a = ttp (center point) to ambient = ~2.4 c/w a c = contact area centered between the two ttp attach points = 30 mm x 30 mm. figure 22. 82443bx thermal transfer plate (reference only) figure 23. 82443bx thermal transfer plate detail rivets for pcb mounting bx ttp 1.000 0.89 3.150 1.050 6.280 3.569 note : all tolerances are 0.015 mm unless otherwise noted.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 56 datasheet 243356-005 figure 24. cpu thermal transfer plate (reference only) 6.3 mobile module physical support 6.3.1 mobile module mounting requirements three mounting holes are available for securing the mobile module to the system base or the system electronics. see figure 18 for mounting hole locations. these hole locations and board edge clearances will remain fixed for all intel mobile modules. all three mounting holes should be used to ensure long term mechanical reliability and emi integrity of the system. the board edge clearance includes a 0.762-mm (0.030 inches) wide emi containment ring around the perimeter of the mobile module. this ring is on each layer of the mobile module pcb and is grounded. the hole patterns also have a plated surrounding ring to use a metal standoff for emi shielding purposes. standoffs should be used to provide support for the installed mobile module. however, the warpage of the baseboard can vary and should be calculated into the final dimensions of the standoffs used. all calculations can be made with the intel ? mmc-2 standoff/receptacle height spreadsheet . information on this spreadsheet can be obtained from your intel field representative. figure 25 shows the standoff support hole details, the board edge clearance, and the dimensions of the emi containment ring. no components are placed on the board in the keep-out area.
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 57 figure 25. standoff holes, board edge clearance, and emi containment ring 6.3.2 weight the pentium iii processor mobile module featuring intel speedstep technology weighs approximately 56 grams. hole detail, 3 places 0.762 mm w idth of em i containment ring 1.27+/- 0.19 mm board edge to emi ring 2.54+/-0.19 mm keep-out area 3.81+/-0.19 mm board edge to hole centerline 3.81+/-0.19 mm 4.45 mm diameter grounded ring + 0.050 mm - 0.025 mm hole diameter 2.413 mm
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 58 datasheet 243356-005 7.0 thermal specification 7.1 thermal design power table 30 provides the typical thermal design power (tdp) specifications. the typical tdp is the typical power dissipation under normal operating conditions at nominal v_core (cpu power supply) while executing the worst case power instruction mix. this includes the power dissipated by all of the relevant components. during all operating environments, the processor junction temperature, tj, must be within the specified range of 0 c to 100 c. the power handling capability of the system thermal solution may be reduced to less than the recommended typical tdp with the implementation of firmware/software control or "throttling? that reduces the cpu power consumption and dissipation. notes: 1. the processor temperature, t j , must be within the special range of 0 c to 100 c. 2. tdp module is a thermal-solution design reference point for the system thermal solution readiness for total module power. table 30. thermal design power (tdp module ) specification typical 750/600 mhz typical 700/550 mhz typical 650/500 mhz typical 600/500 mhz notes 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 1.60v 1.35v 20.0w 13.9w 19.1w 13.4w 17.8w 12.2w 16.6w 12.2w module = core + 82443bx + vr
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 59 8.0 labeling information intel mobile modules are tracked in two methods. the first method is by the product tracking code (ptc), which intel uses to determine the assembly level of the mobile module. figure 26 shows where the ptc can be found on the mobile module. the ptc contains 13 characters and provides the following information. example: pmm75002101aa key: aabcccddeeeff definition: aa- processor module = pm b- pentium iii processor mobile module featuring intel speedstep technology = m ccc- speed identity = 750/600 mhz, 700/550 mhz, 650/500 mhz, 600/500 mhz dd- cache size = 02 (256k) eee- notifiable design revision (start at 001) ff- notifiable processor revision (start at aa) note: for other intel mobile modules, the second field (b) is defined as: pentium ii processor mobile module (mmc-1) = d pentium ii processor mobile module (mmc-2) = e pentium ii processor mobile module with on-die cache (mmc-1) = f pentium ii processor mobile module with on-die cache (mmc-2) = g celeron ? processor mobile module (mmc-1) = h celeron ? processor mobile module (mmc-2) = i pentium iii processor mobile module (mmc-2) = l celeron ? processor (0.18 ) mobile module (mmc-2) = n
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 60 datasheet 243356-005 figure 26. product tracking code the second tracking method is by a system designer generated software utility. four strapping resistors located on the mobile module determine its production level. if connected and terminated properly, up to 16 module-revision levels can be determined. a system designer generated software utility can then read these id bits with cpu ids and stepping ids to provide a complete module manufacturing revision level. for current ptc and module id bit information, please refer to the latest intel mobile module product change notification (pcn) letter, which can be obtained from your local intel field representative. secondary side of the module intel serial number intel assembly identification product tracking code isyww6666 pba xxxxxx-xxx xxxxxxxxxxxxx
pentium ? iii processor mobile module mmc-2 featuring intel ? speedstep ? technology 243356-005 datasheet 61 9.0 environmental standards the environmental standards are defined in table 31 . table 31. environmental standards parameter condition specification temperature cycle non-operating operating -40 c to 85 c 0 c to 55 c humidity unbiased 85% relative humidity at 55 c voltage v_5 v_3 5.0v 5% 3.3v 5% shock non-operating unpackaged packaged packaged half sine, 2g, 11 ms trapezoidal, 50g, 11 ms inclined impact at 5.7 feet/s half sine, 2 ms at 36 inches simulated free fall vibration unpackaged packaged packaged 5 hz to 500 hz, 2.2-grms random 10 hz to 500 hz, 1.0 grms 11,800 impacts 2 hz to 5 hz (low frequency) esd damage human body model non-powered test of the mobile module only for non- catastrophic failure. the mobile module is tested at 2 kv and then inserted in a system for functional test.

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